数字式竞赛抢答器设计VHDL代码Quartus仿真
名称:数字式竞赛抢答器设计VHDL代码Quartus仿真
软件:Quartus
语言:VHDL
代码功能:
数字式竞赛抢答器设计
设计个可容纳四组参赛的数字式抢答器,每组设一个按钮供抢答使用。抢答器具有第一信号鉴别和锁存功能,使除第一抢答者外的按钮不起作用;设置一个主持人复位按钮,主持人复位后,开始抢答,第一信号鉴别锁存电路得到信号后,用指示灯显示抢答组别,扬声器发出2~3秒的音响
设置犯规电路,对提前抢答和超时答题(例如3分钟)的组别鸣笛示警并由组别显示电路显示出犯规组别
设置一个记分电路,每组开始预置10分,由主持入答对次加1分,答错一次减1分
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
设计文档:
1.工程文件

2.程序文件




3.程序编译

4.RTL图

5.仿真图
整体仿真图


抢答控制模块仿真图






显示模块仿真图



部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; --抢答控制模块 ENTITY qiandda_ctrl IS PORT ( clk : IN STD_LOGIC;--时钟10HZ reset_n : IN STD_LOGIC;--系统清零 start_p : IN STD_LOGIC;--主持人复位开始抢答 key_1 : IN STD_LOGIC;--1组抢答按键 key_2 : IN STD_LOGIC;--2组抢答按键 key_3 : IN STD_LOGIC;--3组抢答按键 key_4 : IN STD_LOGIC;--4组抢答按键 LED_tiqian : OUT STD_LOGIC;--提前抢答指示灯 alarm : OUT STD_LOGIC;--报警提示信号 LED_1 : OUT STD_LOGIC;--1组抢答组别指示灯 LED_2 : OUT STD_LOGIC;--2组抢答组别指示灯 LED_3 : OUT STD_LOGIC;--3组抢答组别指示灯 LED_4 : OUT STD_LOGIC--4组抢答组别指示灯 ); END qiandda_ctrl; ARCHITECTURE behavioral OF qiandda_ctrl IS constant s_idle : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; constant s_start : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; constant s_tiqian_1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; constant s_tiqian_2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; constant s_tiqian_3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; constant s_tiqian_4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110"; constant s_qianda_1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111"; constant s_qianda_2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000"; constant s_qianda_3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001"; constant s_qianda_4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010"; constant s_huida_time : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011"; SIGNAL alarm_overtime : STD_LOGIC;--超时答题报警 SIGNALalarm_normal : STD_LOGIC;--正常抢答提示 SIGNALalarm_tiqian : STD_LOGIC;--提前抢答报警 SIGNAL state : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL huida_time : STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000"; SIGNAL LED1234 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; BEGIN --超时答题报警 or 正常抢答提示 or 提前抢答报警 alarm<=alarm_overtime or alarm_normal or alarm_tiqian; PROCESS (clk, reset_n) BEGIN IF ((NOT(reset_n)) = '1') THEN state <= s_idle;--系统清零 ELSIF (clk'EVENT AND clk = '1') THEN CASE state IS WHEN s_idle =>--空闲状态,还没开始抢答 IF (start_p = '1') THEN--开始抢答按键 state <= s_start; ELSIF (key_1 = '1') THEN--1号提前抢答 state <= s_tiqian_1; ELSIF (key_2 = '1') THEN--2号提前抢答 state <= s_tiqian_2; ELSIF (key_3 = '1') THEN--3号提前抢答 state <= s_tiqian_3; ELSIF (key_4 = '1') THEN--4号提前抢答 state <= s_tiqian_4; ELSE state <= s_idle; END IF; WHEN s_start => IF (key_1 = '1') THEN state <= s_qianda_1;--1号抢答 ELSIF (key_2 = '1') THEN state <= s_qianda_2;--2号抢答 ELSIF (key_3 = '1') THEN state <= s_qianda_3;--3号抢答 ELSIF (key_4 = '1') THEN state <= s_qianda_4;--4号抢答 ELSE state <= s_start;--倒计时 END IF; WHEN s_qianda_1 => state <= s_huida_time;--回答时间计时 WHEN s_qianda_2 => state <= s_huida_time;--回答时间计时 WHEN s_qianda_3 => state <= s_huida_time;--回答时间计时 WHEN s_qianda_4 => state <= s_huida_time;--回答时间计时 WHEN s_huida_time =>--10Hz时钟计数650对应65秒 IF (huida_time >= "1010001010") THEN--大于65s后回到空闲状态 state <= s_idle; ELSE state <= s_huida_time; END IF; WHEN OTHERS => END CASE; END IF; END PROCESS; --控制回答计时60s PROCESS (clk, reset_n) BEGIN IF ((NOT(reset_n)) = '1') THEN huida_time <= "0000000000"; ELSIF (clk'EVENT AND clk = '1') THEN IF (state = s_idle) THEN huida_time <= "0000000000"; ELSIF (state = s_huida_time) THEN--回答计时 huida_time <= huida_time + "0000000001"; END IF; END IF; END PROCESS; --控制提前抢答报警信号 PROCESS (clk, reset_n) BEGIN IF ((NOT(reset_n)) = '1') THEN alarm_tiqian <= '0'; LED_tiqian<='0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (state = s_tiqian_1 OR state = s_tiqian_2 OR state = s_tiqian_3 OR state = s_tiqian_4) THEN alarm_tiqian <= '1'; LED_tiqian<='1'; END IF; END IF; END PROCESS;
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